A Conversation about The Importance of Package Design for Chiplet Integration

Chiplets are the new “It” heterogeneous integration technology. Many believe they provide the solution to power, performance, area and cost (PPAC) for everything from mobile computing and automotive applications, to 5G, high-performance computing, and artificial intelligence. In this podcast episode, Françoise speaks with 3D InCites’ Community Members, Kevin Rinebold of Siemens EDA, and Robin Davis of Deca to explore how successful chiplet integration begins with a collaborative design flow. 

To get started, we’ll get some of the chiplet back-stories, beginning with the advantages of disaggregating SoC into hardened IP blocks of different nodes, and reintegrating them on an “interconnect fabric.” From there, we define what we mean by chiplets, what differentiates them from system-in-package, and how different advanced packaging architectures can be implemented to create chiplet packaging.  We also discuss the main challenges of designing chiplet packages; such as who owns the design? Is it the IC designer or package designer? How do we manage the die shift? How do we manage multiple designs?

Additionally, Kevin and Robin talk about their companies’ respective design kits, and how they are working together to enable a chiplet ecosystem.

Papers/presentations referenced by Kevin and Robin include: 

Using a System Technology Co-Optimization Approach for 2.5/3D Heterogeneous Semiconductor Integration – Siemens EDA 

Adaptive Patterning Techniques for the Chiplet Era – Deca 

Contact the Speakers on LinkedIn:
 Kevin Rinebold
Robin (Gabriel) Davis

Kiterocket
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Transcript

Kiterocket Promo: 0:01

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Francoise : 0:21

Hi there, I'm Françoise von Trapp, and this is the 3d InCites podcast. So, Chiplets are the new"It" heterogeneous integration technology. Many believe they provide the solution to power, performance area, and cost for everything from mobile computing and automotive applications to 5G, high performance computing and artificial intelligence. In this podcast episode, we'll explore how successful chiplet integration begins with a collaborative design flow. Today. I'm talking with Kevin Rinebold of Siemens EDA and Robin Davis of DECA about the two companies collaborative work in this area. So welcome Kevin and Robin. Can I get you to each tell me a little bit about your background in this area. Uh, Kevin, why don't you get started?

Kevin Rinebold: 1:09

Sure. Thanks Francoise. So yeah, this is Kevin Rinebold. My role with Siemens EDA is as a technology manager focused on our advanced packaging solutions. So in that role, I work closely with our customer base, both in the commercial, as well as mil/aerospace segment helping them get educated on our technology, helping them to adopt our technology. I've been at Siemens EDA/Mentor for about five years. Prior to that, I was at other EDA companies managing their packaging products, all tolled, I've been involved in packaging for almost 30 years. Going back to some of the early days of the BGA, working with some of the emerging OSATS to, uh, to really develop design tools for the packaging market at that point.

Francoise : 2:01

Okay, Awesome. And how about you Robin?

Robin Davis: 2:03

I have spent my entire engineering career in the packaging world. I actually started with an internship at Lattice Semiconductor when I was still in my undergrad program. At Lattice, I actually met the folks at DECA doing a collaborative project with them. So that's how I knew them. And eventually ended up here. In between Lattice and DECA. I worked for Mentor Graphics at the time. I was in their technical marketing team specifically focused on the package design tools. So working with customers and the internal developers to help drive the direction of those tools. I do a similar thing here at DECA. I work with our customers, both the front-end design customers, as well as the manufacturing customers that we have to help drive the direction of specifically AP Studio, which is our front end tool. Then I also work a lot with like folks like Kevin to help integrate our tool with other design tools so that the design customers can have kind of more of a seamless flow.

Francoise : 3:28

Okay. So I feel like even from my early advanced packaging career in the media space, package, co-design was just starting to be talked about and it's really come a long way. And I feel like this is really where it's going to take off. I mean, we've been hearing about chiplets, i'm thinking maybe six or eight years. And I remember being at Georgia Tech and Subu Iyer talking about how dis-aggregating the system on a chip and integrating hardened IP blocks of different nodes on an interconnect fabric. And then he started chips at UCLA on the concept. DARPA got into this area and launched it s c hips program on the same concept. And now we're seeing Intel AMD and TSMC al l g etting into the game. So, you know, what is the big deal about Chiplets?

Kevin Rinebold: 4:20

Francoise, I think you touched upon some of the high-level points there, right? I mean, a lot of it has to do with dis-aggregating a monolithic system. It seems like you can look at any publication these days and there's talk about the risk and the costs, keep going to the advanced node and scaling from seven to five to three, and that really starts to limit the number of companies, the number of applications, that can take advantage of that. So, and you could probably count them on one hand in most cases. So how do we continue to upscale it? And it's this aggregation of that IP into its individual hard blocks, if you will. And then you need some way to integrate that. So when we talk about chiplets, uh, especially when I talk about chiplets with customers, the first thing we'll do is we'll establish a baseline, is what do you think a chiplet is, right? Because I think sometimes there is just a little bit of a misnomer there where people will say we're doing chiplet design and truly what they mean is a co package design. You know, some type of a set for a BGA type package. When we talk about chiplets, we're talking about, you know, die that are specifically designed to work with other chiplets that are integrated at the package level. And there's some specific connotations to that. A lot of it has to do with, how are these die communicating with one another? There are various types of interfaces, you know, like HBM, AIB from Intel,, to facilitate this communication. So, that's really what we see as one of the bigger differentiators for chiplets. All tolled, we see many of the companies that you identified earlier, moving in this direction very quickly. We see a lot of government programs, either DARPA sponsored, or some c ollaborations around some of the Chips for America Act money that's going to b ecoming available, you know, all about how do we enable a chiplet ecosystem that's onshore with a trusted supply chain.

Francoise : 6:43

Um, you know, you bring up a really good point. We always get into nomenclature on 3D InCItes and we want to be sure and clear about what chiplets are. I've also heard them referred to as"dielets". Are these interchangeable o r i s there a difference between what is a dielet and what is a chiplet?

Kevin Rinebold: 7:06

I can only answer it from my personal opinion, I would say no. I think that's always one of the challenges that we have in talking with customers is to do some type of level setting exercise to understand what their perception of the term is. Chiplets- Dielets- we have customers who refer to them as tiles. I think one of the first steps of any of those conversations is just to do a level set, make sure that there's some alignment on understanding of the technology.

Francoise : 7:38

Okay. Also I was thinking about along those lines of what you were saying is what are the advantages of integrating IP blocks of different nodes? I mean, why not just do everything in 3nm or everything in 5nm?

Kevin Rinebold: 7:55

Well there are a number of issues, right? I mean, one is when we start looking at big processors for machine learning, artificial intelligence, high-performance compute, the devices can get quite large, to the point where they're pushing the reticle limits, of masking and manufacturing equipment. Um, one of the big concerns of doing that is yields: The larger the die the fewer of value on a wafer, and your yield starts to drop off. So that's always one of the underlying concerns is maintaining an acceptable level of yield. The other issue too, is that there are certain types of IP that there's a diminishing return from taking them to an advanced node? So a lot of your memory control your IO controllers, even some of the high-speed interfaces really don't benefit from going to advanced node, like a three nanometer or five nanometer. There have been plenty of examples out there from AMD and others where they've shown some of their chiplet designs where they'll leverage the advanced technologies or the advanced nodes for their cores maybe using a seven nanometer for their cores, but then they'll use a 16 nanometer process for the IO. So, so those are some of the factors that go into making that decision.

Francoise : 9:15

This might play into when you talk about the difference between Chiplet integration and just a SiP. Do chiplets mostly refer to the compute versus we're not integrating a MEMS device or an RF device, or an analog and a digital. That's a system in a package that's not necessarily a chiplet integrated package. Correct?

Robin Davis: 9:37

I absolutely agree.

Kevin Rinebold: 9:40

I wouldn't say definitively they're mutually exclusive, but for the most part, you know, it seems to be aligned that, we're integrating CPU's with memory, um, you know, some of the interface logic that goes with that, that's typically what we are seeing today.

Robin Davis: 10:00

And I think it kind of goes back to what Kevin said earlier that it really has to do with how the chip is designed to be used. So while they're not mutually exclusive, we haven't seen chips that are being designed for that use case yet to specifically be used in a chiplet solution. So the integration requires more design work to make those two chips work together because they weren't designed to be in that type of package.

Francoise : 10:36

Okay. Whereas when you're, dis-aggregating a system on a chip, they were designed the functionalities, I guess that's the word I was looking for is functionalities. In the system on a chip, you have segments of different functionality, all designed into one chip and working together. And what we're doing is we are breaking this up into separate IP blocks and then reintegrating them onto some sort of interconnect fabric, an interposer or something with, um, some intelligence built in. I mean, we're not just putting them on an FR4?

Kevin Rinebold: 11:13

Yeah, you're absolutely right. It's that there's going to be things like driver strength, for example, that the driver strength f or a device designed in a chiplet doesn't need to be anywhere near as powerful as if it was being implemented in a n ASIC. If it was going into an ASIC, it would ha ve t o be strong enough to drive a signal through the die, through the package, off onto a printed circuit board and in to t he receiver on the other end of the connection. Whereas on a chiplet, these things are within a couple of m illimeters of one another, your driver strength doesn't have to be as s trong. So what does that mean? Well, it means a m uch lower part de vice, right? So this is a good example of where you are designing chiplets to be in close proximity to other chiplets. I think that's probably the simplest example.

Francoise : 12:09

Okay. So it can fan out wafer level packaging, SiP, 2.5D, 3D ICs. Can they all be implemented? These architectures can all be implemented using chiplets.

Kevin Rinebold: 12:20

I think at some level any of those types could be used for chiplets. What it really comes down to is, the limiting factor really is going to be bumped density. And one of the big influencing factors on bump density is the type of interfaces that are being used to communicate, die, to die. You may have a highly parallel interface like HBM for HBM memory or Intel's AIB, uh, interface. And they're going to require a much finer bump to give you some idea, we're talking about bump pitches 30 to 80 micron range and that's what's needed to get the appropriate level of density. So that in itself is going to become somewhat of a gating factor for your substrate options. And I think for the most part today that would imply some type of interposer technology, whether it's Silicon or organic, may imply some type of bridge. You may employ some fan out technology. Like, what the folks at DECA are doing now, comparatively speaking, if you look at a serial interface, like ultra short reach or extended short reach, XSR USR, they're going to require a little bit coarser bump pitch, somewhere in the 90 to 130 micron range, and that then opens up a much broader set of substrate options, more of your conventional, you know, laminate FR4-type substrates.

Robin Davis: 13:53

Yeah. We did a collaborative paper, Siemens, EDA, and DECA for IMAPS DPC last year. And we actually looked at a 10 chip chiplet solution. And we compared the differences between using an interposer. I mean, interposers are kind of the defacto industry standard for chiplet solutions right now. But what we were exploring was going to smaller pitches with fan out. So, um, DECA"s next generation that they're coming out with for their design rules for M series with adaptive pattern and goes down to 20 micron pitch array ability. It's never going to quite catch up to interposers, but it's getting there. So these other technologies are coming up with ways to provide more cost-effective ways to integrate pitch on the die is kind of the limiting factor like Kevin said.

Francoise : 15:03

So how much is cost a driver of whether or not you use chiplet integration, like with 3DIC? It all started with high-performance computing. Are we following that same path with Chiplets?

Kevin Rinebold: 15:15

I think if I understand your question correctly, I think it is to some extent. I saw a paper recently from AMD. It was presented at one of the more IC-oriented conferences, that they actually did a cost comparison between a monolithic versus a chiplet. And I think they determined that the chip with implementation-- and don't hold me to these numbers, but I think it was on the order of 40% cheaper than the monolithic implementation with a 10% increase in overall area. Right. So it was a little bit bigger package, but a much lower cost and a big partial portion of that was due to, let's say having one big monolithic chip, they broke it up into four pieces and then they implemented them as chiplets on a substrate. So it comes back to that whole wafer yield, that that we talked about earlier.

Francoise : 16:11

So in this case then for instance, back in the, you know, when we were first trying to launch 3d ICS with TSVs, it was more cost-effective to do, you know, still do wire bond or still do flip chip. It was still too expensive, but now we're comparing that, not with the packaging side, but with the monolithic and with Moore's law. So it's more cost-effective way and that sense we're being more cost-effective. Okay. So, let's talk about what are some of the main challenges of designing chiplet packages and do we even call them, oh, do we even call them chiplet packages?

Kevin Rinebold: 16:51

I do- I think that's socially acceptable. Robin, I'm sure you got some thoughts on this?

Robin Davis: 17:04

Yeah, yeah, absolutely. So we talked about these smaller pitches and that you definitely end up with a lot of congestion around those areas and breaking those out. If you're not going to just use an interposer, you're talking about probably multiple redistribution layers to escape those signals for traditional fan out packaging, they require an additional copper pad. I don't know how familiar you are with die shift and fan out, but, they require a large copper pad for the die bumps so that when that die shifts and rotates, it still makes connection. And that kind of limits the amount that you can reduce pitch because you can't have those pads run into each other. So you end up with this congestion problem around die pitch. Deca's approach to that is adaptive patterning. But T SMC i s approach is that they have an entire layer just for those extra pads. And then with interposers, I mean, the main downside is going to be the cost. So that's one area that it gets tricky. Other factors to take into account are g oing t o have to do with power delivery and signal integrity. Meeting all of the design rules for routing and H BM interface on such a small scale and t hen few layers can be challenging.

Kevin Rinebold: 19:05

I have a little bit different perspective as, as a software vendor, as a supplier, right? So when we look at the challenges associated with chiplet technology, we really see it as disruptive. I've been referring to high density of advanced packages being disruptive. When I talk about disruption, I'm talking about how it impacts tools, the methodologies, you know, the overall ecosystem. And I think with chiplets, one of the first question is who owns the design process, right? Because it is seemingly Silicon centric. So for some organizations that implies that the IC design teams own the chip design process. But what's different is you have multiple die instead of a single dice. So that then would imply that folks like in the packaging organization, and maybe even in some companies, even a PCB organization are better aligned to handle these types of designs. And, quite honestly, we don't see one c lear c ut methodology winning out at this point. We do see a little bit of both. So with that also then becomes, what type of tools are being used, right? So when we talk about an I C team doing chiplet design, you know, they're going to gravitate towards using traditional I C placement, route tools and producing GDS files or OASIS files to give to, to folks like Deca. If it's more of a packaging team, it's going to be using the conventional p ackaging d esign tools from Siemens or, or other folks like that. In the latter, the other piece that comes into it then is, you know, do those tools have the capacity to handle some of these chiplet designs. Robin referenced a paper that she did. I forgot what the total pin count of that design was, but we're seeing chiplet designs where, you know, we're dealing with 500- 600,000 total pins. So that can definitely challenge the CAD tools.

Robin Davis: 21:17

I think that's kind of the beauty of the co-design piece that Francoise mentioned at the beginning. WIth Siemens XSI expedition substrate integrator, you can manage multiple designs from within one, kind of hierarchy. And so, like we were talking about in a recent meeting, if you start having things like fan out with multiple embedded die and then die on top of that and potentially below that as well, you end up with different levels of design, possibly multiple fan out RDL structures, maybe a substrate underneath that. Um, and being able to manage all that connectivity from one place and possibly even having some of the like left def from the die layout in there, um, is extremely helpful, but then being able to have each of those designs done in there, like if you're using XSI, you're gonna use expedition package designer, you'd have a different design database for each individual layout. So you don't have these giant clunky designs that all of the layers in there. And like Kevin said, you're still going to have these large pin counts. So though those individual designs are still going to be quite large, but at least you don't have to have every component in the one database.

Kevin Rinebold: 23:00

Yeah. And, just as a followup to that too, is there's a lot of different methodologies when it comes to how we do design. And, I think collectively when we look at designing one die in one specific technology, you know, we, talk about design technology, culture optimization, and you talked about at the beginning of the discussion here about, you know, how do we optimize this device for power, performance area and cost. Yeah. And it's, you know, like I said, it's been a designed specific, you know, where we optimize that technology to Robin's point, you know, when we get into diet, now it becomes a system technology, culture optimization exercise, or what we call S TCO, where we have to balance competing requirements across multiple technologies. You know, it's not just one diet at one process note, it's multiple in different process nodes and they all have some unique characteristics.

Robin Davis: 24:01

Right. So I think that's one of the other challenges. And another one I would like to point out too, cause we've talked more about processes. We've talked about tools, there's a whole other element of standardization in the ecosystem. How do we communicate chiplet data within that ecosystem and within that provide the needed use of the information, not just the electrical representation, but the various thermal models, electrical models. So when we are doing this, you know, system technology cooptimization, I c ould start to do some predictive modeling. I can find out if the gradients from the die are causing some thermal shadowing, causing my H BM to go out of tolerance. The good thing is is that there are some efforts underway, right? Y ou, you have stuff like, I think it's called ODSA you know, they have a subgroup called CDX o r which is trying to standardize on a chiplet design exchange format to, to define what that file format looks like, what the content is included. You know, so, so there is light at the end of the tunnel, but we're just at the beginning trying to define what t hese standards need to look like.

Francoise : 25:16

So is this requiring specific or a special set of tools, because before you were talking about how IC designers want to rely on IC tools, and the package designer wants to rely on packaging tools ot it is a matter, is it a matter of collaborating with those different types of tools or are we looking at a whole new suite of design tools that are targeted for specifically for chiplet integration?

Kevin Rinebold: 25:42

Yeah. So I think, at least from a Siemens perspective, I think the key is having flexibility and adaptability. We have a pretty broad product portfolio, you know, so if we have a IC customer the are bent on doing an IC design flow, y ou k now, we have P NR tools that can support that. And we w ork closely with them, likewise, on the packaging side, but there are some, there's pros and cons, right? So for example, when you were dealing with an IC place and routhe tool, those are geared towards a single technology, a single device, when millions of transistors that they have to manage, but it is one, one process technology, one device. So when we get into situations where we have multiple die, you know, let's say we have an SOC and you have some, you know, you have f our HBM. I have to basically f latten t hat design. So the ICP and our tools can understand that because it has no concept of different. So the ICP and our tools have the capacity. They have the awareness of some of the Silicon oriented rules, but they really don't understand multiple devices. Well, you know, so you have to basically fool it or collapse the data or f latten t hat data. Conversely the packaging tools, in my opinion, are probably a little bit better poised to deal with these types of designs, because it understands enough about the IC process and understands the various I C formats like left up a nd GDS and Verilog, and has t he data capability to deal with multiple devices, and, have a correct by construction methodology. So, u m, I, I t hink the jury's out as to what the, what predominately is going to be the tools, but at least what we're seeing today is that it tends to be more of s ome of the packages during it, the to ols l eading the way.

Robin Davis: 27:35

Yeah. I would say what I primarily see as package design tools, some designs that are coming in, like working with the manufacturers. Sometimes they get designs in GDS format and then they choose to import that into the package design tools so that they can work with it. So I do think it's skewed that way slightly. And I do also see, from multiple tool vendors, this kind of idea of having a co-design space as a way to enable the die designers to play around in the packaging world without getting too far out of their comfort zone. U m, but then still having the end database in a place where the manufacturers who are package designers can use the tools that they're comfortable with.

Francoise : 28:38

So it seems like with chiplets we've really come to the pinnacle of a good reason for chip package co-design and then we have now, Siemens has their package design kits, right. And DECA has it's adaptive patterning design kits. Yes. Um, These are two separate things or a sub one is a subset of the other?

Robin Davis: 29:07

They're two separate things. We may incorporate components of them because we do make our APDK is customer specific. So if we have a customer who wants us to include functionality that we've specifically come up with with Siemens, we could include that like drop down menus, things like that. NRA PDKd. We have our own tool, suite AP studio, is our front end tool. And so that's what we're delivering. And that tool basically takes the design from a unit design and makes it a panel level design. So all of the unit design is really still being done in one of the EDA vendors, other EDA vendors tools. Um, so, so that's where those two design kits are really separate.

Francoise : 30:05

Okay. That makes sense. And so the, the adaptive patterning design kits specifically for the adaptive patterning, integrating the adoptive patterning process into your package design.

Robin Davis: 30:20

Correct. Because adaptive patterning, well currently it's only being licensed and used with our M series technology. It could be licensed by anyone. So if TSMC wanted to use it on InFO, we could provide them with the, we would use AP studio with them as well.

Francoise : 30:40

So how does AP studio work?

Robin Davis: 30:43

Um, it's it's taking your unit design and it's creating the entire panel map. Its identifying areas that need to shift and rotate with the die like I talked about earlier, that's how we deal with dice shift. Um, and then it's also identifying the areas that need to be adaptively routed during manufacturing, so it generates a bunch of information that then goes to AP engine, which is the tool that they use on the manufacturing floor, to do that on the fly adaptive routing and adaptive alignment.

Francoise : 31:25

Okay. Kevin, what about Siemens package,design kits and the program that you guys launched once you talk a little bit?

Kevin Rinebold: 31:35

Um, so first of all, I mean, we w we will refer to these as PDKs. We will refer to these as ADKs your process design kits, assembly design kits. And recently I've had people start to call them CDKs, chipper design kits. From a vendor's perspective, they're all basically the same thing. You know, how do we enable the technology for their customer base? So typicall in these kits, you're going to have some rule checking mechanism, for that prticular process, we would refer to this as a Rule Deck. So there's tools out there, like our Calibre product, that is pretty much like the standard tool out there to check GDS before you go off and build the masks. It's pervasive in the Silicon world is becoming prevalent in the packaging world. So one of the things that some of the vendors are providing are the input file rule decks to use this product. Companies like TSMC and Samsung and others actually even mandate that the designs be checked using this methodology. So the rule decks tend to be one of the first pieces of a design kit. From there, you get into design templates, these are basically the starting point for design, pre-populated with the appropriate constraints, the layer stack ups materials information, from there can expand out, it can maybe include, some custom functionality like AP studio, and then even beyond that, then we can start to look at things like compliance kits for the different interfaces to verify that the design is within tolerance, you know, for that particular interface. The other comment I will make about the rules is what's interesting is that there's a lot of concern by the manufacturers, in the OSAT space predominantly about exposing their process IP, r ight? So instead of just providing a rule deck that anybody can read and interpret, a lot of these rule decks a re encrypted, so th at w a s a mechanism for them to protect their IP. So these are all, some of the content that you would see in a PDK. Um, w hat we did is we launched Si emens D J l aunched a couple of y ears ago, something called the OSAT Al liance p rogram. This is our way of working with, OSATS you know, at the time with DE CA A mkor ASE, Samsung TSMC, t o enable their particular technologies within a Siemens EDA tool. So supporting tools like Calibre, supporting tools like Expedition, for their particular processes. And that continues to be the case today.,I would anticipate, new members coming on boar as we start to see the chiplet ecosystem, ex pand.

Francoise : 34:35

So that kind of brings me to my final question. What is the relationship then now between Siemens EDA and DECA? How are you guys working together to enable chiplet design?

Robin Davis: 34:47

Yeah. we are actually working very closely together. Kevin and I had spoken a lot recently. We're working on a collaborative project to kind of advance these PDKs on Siemens side, and APDKs on our side to really have a seamless flow. We want the customers that are doing the front end designs to do so with ease. We don't want it to feel any more complicated than a traditional package design. So we're trying to implement a lot of automation, to kind of work around those challenges we were talking about earlier specifically with DECA, because we have adaptive patterning there's specific to adaptive patterning design rules. That can be quite complicated. We don't want the designers to really have to think about those too much. So we're working really closely to implement those kinds of in the, in the background and make it a much smoother design process for the customers. Okay.

Francoise : 35:58

Awesome. If people want to learn more, how do they, what's the best way for them to get in touch with each of you

Robin Davis: 36:06

I'm readily available through LinkedIn? So please feel free to reach out to me, connect with me, message me. I check it regularly.

Kevin Rinebold: 36:16

Yeah. and same for me. Right. I'm active on LinkedIn, so you can find me there and then also, u h kevin.rinebold@siemens.com.

Francoise : 36:26

And I think we have a white paper on this topic from Siemens that's currently on our homepage.

Kevin Rinebold: 36:32

Yeah, I think so. I, if I remember correctly, I think that's the one related to system technology co optimization- STCO- we talked about earlier,

Francoise : 36:41

Check out the white paper. I will put contact information in the show notes page of the podcast. And I would like to thank both Kevin and Robin for joining me today and sort of demystifying the chiplet story. Thanks so much. Thank you.

Robin Davis: 36:59

Thanks,

Francoise : 36:59

We'll talk to you again soon.

Robin Davis: 37:03

Bye-bye

Francoise : 37:08

There's lots more to come. So tune in next time on the 3D InCItes podcast,

Speaker 5: 37:25

[inaudible].