From Tape-Out to Co-Design: The Evolution of 3DIC Technologies

Pratyush Kamal explains how 3DIC technologies are transforming semiconductor design as Moore's Law slows, requiring closer integration between chip and package design to maximize performance.

• Traditional chip design treated packaging as an afterthought with designers "throwing designs over the wall"
• Economic realities of advanced nodes mean companies now pay more for smaller transistors, driving chiplet adoption
• Thermal challenges multiply in 3D stacks as power density doubles with each added layer
• Data centers projected to consume 10% of US electricity by 2030, making power efficiency critical
• Siemens working to standardize design languages across tools and enable open chiplet ecosystems
• Average age of electrical engineers in US is 57, creating urgent need for workforce development
• Universal Chiplet Interconnect Express (UCIe) emerging as key standard for chiplet interoperability

Visit siemens.com/3DIC to learn more about Siemens' comprehensive 3DIC solutions.

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Transcript

Francoise von Trapp : 0:02

Looking to stay ahead in the chiplet revolution. With 3DICs transforming everything from AI to mobile and data center design, Siemens EDA is making it easier than ever to manage complexity and accelerate innovation. Their comprehensive 3DIC solution brings together architecture, exploration, thermal analysis, verification and co-design all in one unified platform. If you're navigating multi-die systems, this is the competitive edge you've been waiting for. Visit siemenscom slash 3DIC to learn more. Hi there, I'm Francoise von Trapp, and this is the 3D Insights Podcast. Hi everyone, you know if we've heard it once, we've heard it a hundred times on this podcast. 3dic using advanced packaging technologies are critical to achieving power, performance area and cost of next generation semiconductor devices, and it really looks like that next generation that we've been talking about for so long is actually here. It's now. Design engineers know it and they need the support of the EDA or the electronic design automation segment of the industry. So here to talk to me about this important topic is Pratyush Kamal. He's the 3D IC expert, who happens to work at Siemens Digital Industries Software. Welcome to the podcast, Pratyush.

Pratyush Kamal: 1:32

Thank you, Francoise, for having me here.

Francoise von Trapp : 1:35

So, before we dive in, can you tell me a little bit about your background and your current role at Siemens and previous roles that brought you to this point?

Pratyush Kamal: 1:44

Sure, Francoise. So I joined Siemens roughly two years ago. I joined as a contractor, helping Siemens on their government engagements, especially DARPA-driven projects, and then for the last one year I've been a full-time employee and in my current role I'm the Director of Central Engineering Solutions and our charter is really to look at a holistic solution for 3D ICs as well as anything any new technologies that is evolving when we talk about two nanometer and below nodes, because they really are tied to, as far as the usage goes, advanced packaging in some form or the other very intricately. So that's the focus of our current organization. It's a new team that has been put together and we have a lot of subject matter experts, people with different design domain expertise, and I'm, overall, the technical lead for this organization.

Pratyush Kamal: 2:34

And prior to joining Siemens, I had many, many years of experience. I started my career as a design engineer, Then I grappled with EDA industry for a while. Engineer, then I grappled with EDA industry for a while and then I spent 15 plus years designing chips and also defining architecture for the chips as well as the systems. I spent a lot of my career at Qualcomm, a bit at Google as well. It's at Qualcomm, 10 plus years ago that I first got introduced to 3D IC and at the time we were trying to look at a long-term view of 3DIC how eventually, you know, when we look at CFET and stack technologies of the future. We were thinking about it 10 years ago, but we realized the challenges that lay ahead, so we shifted our focus on stacked-based 3DIC, and a great example of that is a hybrid bond-based wafer-on-wafer or chip-on-wafer stack. So we picked that as our research vehicle, but it didn't prevent us from looking at other 3D stack-based integration options.

Francoise von Trapp : 3:31

So you know, when I first got into this industry in 2005, I've always found the design side of things to be very hard for me to grasp. I have an easier time with the physical, you know, and seeing how things are structured. And I remember talking to some of the experts when Siemens was mentor and they were just starting to look at co-design and co-design optimization and this is 20 years ago. And how has that conversation changed? What kind of brought that realization that now it's all this time and you're just developing this actual team to focus on that in the 3DIC space? But can you explain a little bit how that evolution occurred?

Pratyush Kamal: 4:16

The way I look at it, it almost seems like we put this industry as an afterthought. We first discovered the transistor. We manually learned to lay that transistor. All the words we continue to use today, they are all related to manual processes, for example, tape out. There was an actual tape that was involved in the tape out. So we did everything manual. And then one day some of us thought, okay, let's actually try to automate that. Then we built some tools. We started putting more and more complex circuits together.

Pratyush Kamal: 4:45

As long as we were dealing with hundreds of thousands, the need for automation was still small. But the moment we shifted to true VLSI, very large scale integration, where you're dealing with millions and millions, and today we are looking at trillion transistor designs Then we realized we can't do everything manually and over the years the industry drove itself to automation. That evolution happened. But again, if you look at the whole chip design process, it's very complex. It requires expertise from so many different fields. Just the definition of a transistor requires multiple expertise, right, and the amount of analysis the software needed to do that is very diverse in nature, and so that's one reason why the way the EDA industry today is. The design flows are very fragmented.

Pratyush Kamal: 5:31

For the many years now we have talked about RTL to GDS, holistic flows, and if you look at the big EDA organizations, they all have competing solutions in the whole domain, starting all the way from your abstract definition of your system, whether it's System C or whatever, and bringing it all the way down to the GDS that you send to the foundry.

Pratyush Kamal: 5:49

Right, this whole RTL to GDS, in fact it's not even RTL, it's behavioral to GDS. Now we are talking, right, there are so many different pieces of software involved here and they have to be stitched together over the years, forming what I call a patchwork, quilted approach to design automation. So, yeah, it has been a lot of over-the-wall approach because, again, the expertise is so diverse through this whole process. But as the complexities increase and as new tools become available to us tools like artificial intelligence, that's the case in point here we can start to bring some of these boundaries down, walls down. We can start to imagine ourselves as cross-functional experts, even though we don't have that background. But we have these tools at our disposal today that will tomorrow allow us to me, as an electrical engineer, can tomorrow dream to do mechanical simulations. So that's what we are trying to do in 3D IC of today across the industry.

Francoise von Trapp : 6:46

So you're saying what drove this is the need for developing these in higher volumes. The devices are now in such a volume that it can't be done manually. But what if, when they started thinking about not just chip design and designing really complex chips, but when they started realizing that you not only had to think about the chip, you also had to think about the package and the system and maybe work it all the way back so that what you're designing in a chip was going to be able to be carried through?

Pratyush Kamal: 7:20

Yeah, I mean until very recently, if we take the very high performance compute market out, because it's always spearheading in terms of needs by very definition. But my previous experience was in the mobile space and I'll tell you anecdotally, as a silicon designer, we never thought about the package. It was an afterthought. We designed our GDS, we threw it over the wall and then somebody put a mold around it and it worked.

Pratyush Kamal: 7:43

Right right and then somebody put a mold around it and it worked Right. Right, as we started to throttle up our speeds, interface speeds, as our power densities increased, we started to see challenges. So then I mean, even today, most of the package design is done in Windows environment. Roughly 10 years ago was the first time I actually opened a package layout in an EDA tool. I wouldn't name the EDA tool involved there, but for the first time I actually bothered to look at a layout, and the reason for it was because I was the interface architect and we had SI challenges on that interface and it was not a very high speed interface.

Pratyush Kamal: 8:16

We were talking PCIe 3.0 here, very small compared to PCIe 6.0 that we are starting to see. You know, at least in the specification space we are discussing those. What caught me by surprise was that it was actually a Windows-based software. I had never dealt with a Windows-based interface in Silicon design world. It came as a shock Then. That's when I realized how different package design and how uncoupled it is from the Silicon world and how uncoupled it is from the silicon world. And today, as our team looks at co-design and looks at how we can design these chiplets in tandem because they will be used in tandem in an advanced package tomorrow. We have started to realize the gaps that exist. You have to do a lot of data conversion. You have to not only do that, you have to move data across different servers, different file formats and file servers. So we are trying to bridge to decoupled world here through 3D IC engagement Okay.

Francoise von Trapp : 9:15

So it's a very complex challenge to solve, and so I can see where, early on, if you had manual that works, if, until it was volume, there was no need for EDA. So it always seemed to me, like you know, you knew something was approaching commercialization if suddenly there was an EDA tool for it. Right In the beginning, when it was still in R&D, until the EDA tool came along, you knew that something that was manufactured in volumes. But now everything's hopping in a little more close together. We don't seem to be waiting as long to engage the EDA vendors. It seems to be more part of the holistic approach. Is that true?

Pratyush Kamal: 9:55

That is true, and the reason for it again, is the complexity of design. What people realized is that the EDA industry evolves in steps. There'll be innovation and then there would be nothing for the next few years, and then something new will come up. Everybody will jump on the bandwagon and we will evolve, and then the cadence is slow in that sense. Right the place and route tool. Fundamentally, if you look at the core algorithm, it hasn't changed. It has evolved. The fundamental algorithm is still the same as it was 25 years ago and you're very right. Bang on on making that assumption that when the EDA tools appear, you have an indication of what is coming in terms of actual end product.

Pratyush Kamal: 10:32

I'll tell you a direct 3D IC anecdotal story that I have. So I was part of Qualcomm Research and we were working with TSMC at the time, who were using hybrid band 3D-based 3D stack for camera-based applications, image sensing applications. So we had an idea how we can expand this to logic-on-logic 3D application, make it completely generic, right? So we built a couple of test chips. We did not have any CAD tools available to us, so we had to hack everything ourselves and we spoke to a couple of EDA companies at the time on behalf of Qualcomm and we did not get a lot of collaboration because they wanted to first see whether there was any product on the roadmap, whether there was a path to commercialization for this technology.

Pratyush Kamal: 11:21

And we realized very soon that we don't have the budget to spend tens of millions of dollars just for tool development when we have a few thousands of dollars for the product development as part of the R&D. So we had to shelve our 3D ICF for our ambitions 10 plus years ago because of that limitation. What has changed in the last 10 years is A end of scaling On paper. We are still scaling things. We are going from 5 to 4 to 3 to 2 nanometer, but you're not getting the same dimensional shrink Plus. You're not getting it economically. You're actually paying more to build a smaller transistor, unlike in the past.

Francoise von Trapp : 11:58

It seems like it's just being able to say that we can do it. It's not really about Moore's law anymore, it's that can we keep scaling down, but then you also have to look at packaging that right.

Pratyush Kamal: 12:09

Yeah, I'll tell you why. That packaging becomes very critical for smaller technology Because it's a very complex process. The whole way for stack formation is much, much, much more complex. We are starting to use EUV. Formation is much, much, much more complex. We are starting to use UV. We will be very shortly using high-end UV-based solutions for lithography.

Pratyush Kamal: 12:29

The challenge is the industry hasn't yet fully understood the defect mechanism through UV. There is a lot of control issues and we are talking about 22, 24 nanometer pitches here, and you can imagine the stochastic challenges that we have to deal with at that geometry. So what we are seeing is, even though we can yield designs in these technology nodes, the yields are very poor, especially as a dye size grows. There is an exponential correlation to the yield that you'll get the larger the dye, the lower the yield. So now, by definition, for these technologies to be economically feasible, you must limit your die size, otherwise there'll be so many bad dies on your wafer that it would not make sense to you, and that's why the whole industry is moving away from the idea of SOC silicon on chip, where we talked about a monolithic design where all the functionality of the system of the PCB goes inside the die. We are getting incremental scaling advantage in these technology nodes. But there is other advantage that drives the need for these smaller to smaller nodes primarily the performance and power. You may not be able to shrink the area as much, but you are definitely seeing gains in terms of power and performance and especially when we move from one transistor architecture to the next. For example, we will be very soon adopting gate all-around technology. Intel calls it ribbon-fed. The transistor itself will give you better performance, better power performance, but you won't necessarily shrink the footprint of the transistor compared to its fin-fed equivalent. So there are benefits to moving at least some portion of your design to these very advanced nodes.

Pratyush Kamal: 14:17

But then at the same time we realize when you have a logic design you need to have SRAM with it. Now SRAM hasn't really scaled since 5 nanometer. We actually see a growth. It's actually reverse scaling if you compare 3 nanometer SRAM with the 5 nanometer SRAM. When you look at the cost per bit of an SRAM cell, it actually it's been a while. I think 7 nanometer probably was the last node, was the cheapest node and since then we have been paying more per bit of SRAM in our dyes.

Pratyush Kamal: 14:45

So you're forced to do desegregation of the dye. Now that's where the advanced packaging becomes very important, especially 3D stack, because what is happening is because when you chop a dye into two and put it in the same package, now the package is bigger, its footprint on the PCB is bigger. So there are a lot of systems that are space constrained, like a mobile phone. You have only so much of X, y and Z available to you, and that's why 3D becomes interesting.

Pratyush Kamal: 15:12

3d also becomes interesting because, when you put things vertically, the length of the route between those two chiplets are very, very small, non-existent in some cases. They are directly connected through the bump short, micro bump short or the hybrid bump short, so you get a lot more electrical performance out of the design. Through this stack, also, you are gaining on the footprint. The challenge, though, is you're folding the design onto itself. So, for a two-stack 3D, your power is doubling, your density is doubling, so you have thermal challenge combined with power challenge combined with signal integrity challenges, right? So all of that has to be analyzed in tandem for 3D IC, which in the past we didn't do so much.

Francoise von Trapp : 15:53

EDA is really critical to this.

Pratyush Kamal: 15:56

EDA is very critical to this. Yes, yeah.

Francoise von Trapp : 15:59

How has the chip designers world changed, as Moore's law has slowed?

Pratyush Kamal: 16:03

Before we go there, I want to tell you that the way this whole capital industrial base works, right. Okay, you build a perfectly functioning iPhone X and it has four-year longevity. But both from the supplier's perspective as well as from the customer's perspective, there is an expectation built in that we will be upscaling the product every so many years. Right? Every year we want to add more functions and we want to make things cheaper at the same time. But what is happening is, with the slowdown of Moore's law, companies can't quite add functions anymore without exploding the cost of their designs. So suddenly there has been a lot of emphasis and that is again coming from my own personal experience on squeezing everything out of your design. So in the past, because you have a one year cadence to do the design and get it out the door, get it manufactured, get it tested. To do the design and get it out the door, get it manufactured, get it tested, you would leave a lot on the table. As long as the design is implemented fully functionally, you are okay. It didn't matter whether we leave 5% or 10% of area or power on the table. We didn't fully squeeze that out. It was okay. The cadence was more important.

Pratyush Kamal: 17:20

But as things slow down, certainly there is more opportunity now for designers to squeeze more out. So there's a lot of emphasis on optimization and it has the moment. Designers now understand the need and the economic benefit of optimization tangible benefit of optimization suddenly co-design becomes a palatable option for them, right. So so fundamentally, people are getting open to the idea of using cross-functional tools. If I'm a silicon designer, I'm getting more interested in how the package works. Can I save something in silicon through some clever implementation within the package?

Francoise von Trapp : 17:57

And there wasn't that awareness before.

Pratyush Kamal: 17:59

It wasn't that awareness, because we were doing free scaling, we were getting cheap scaling, so we didn't need to.

Francoise von Trapp : 18:07

But there's also different drivers. Now. It's not just the smartphone chips, right, it's also. We're talking about high-performance computing and data centers and all of these places where, like the AI, chips, are really what's driving the industry. How are the end devices impacting at the EDA level?

Pratyush Kamal: 18:25

So definitely the scale is the first concern when you look at the data center-based applications, and the scale doesn't stop at the chip or the package boundary anymore or the rack itself. Right, it's rack to rack. We are talking about data center to data center communication as well. The systems of yesterday were bounded. There were limited size systems versus with cloud as part of our computation platform everywhere, I see our system as limitless. It's like the universe. There's no end to it. So the solution you put in there today you have to think of it in terms of scalability.

Pratyush Kamal: 19:02

All the data center applications are leveraging advanced packaging. It's ushering in new innovations within the package and outside of package as well. A lot of this communication is also employing optical communication. So optics is becoming very tightly integrated with silicon today. So you hear a lot about the co-package optics. So when we do an electrical simulation, we have to think about the optical domain as well and vice versa. And just staying with the conventional chips.

Pratyush Kamal: 19:34

Also because 3D IC doubles your power density and that directly impacts your thermal. We have been thermally limited in all our systems, whether it's the data center, whether it's the mobile phone, more so in the mobile phone than in data center because we have better thermal mitigation options there. But 3D IC doubles that challenge or triples, based on the number of stack that you have, quadruples it there. So you have to be able to do not just the thermal simulation by itself but thermal a rare design right. When you're designing upfront you have to think about thermal very early on. Or when you're doing your thermal you have to understand what is the effect on stress due to it or what is the effect of thermal on the electrical performance of the transistor. You have to do these things more closely Now.

Pratyush Kamal: 20:26

In the past, when we had a single design, we would look at the worst case thermal, do a static analysis and as long as it's meeting the thermal boundary condition specs, we are fine. But today, what is happening? When you do two dye or more in tandem design, there will be thermal coupling between them and as you are doing different design, there could be heat resonance because one dye is wasted, heat is flowing through the other dye, so there could be resonance phenomena occurring in there and we don't understand any of that. We have never simulated that in the past. So that's why the need for multiphysics, dynamic simulation comes in, so the need for computation.

Pratyush Kamal: 21:06

When you're doing these computations, you need a lot more computational resources than you have in the past. So it's really redefining the ADA space, because we can't just keep throwing more and more machines to get a bigger job done. And that's where AI comes into play. Ai is helping us make our simulation runs efficient. Ai is helping us make our simulation runs more user-friendly. We one day hope to see a world where, as an end user I'm an electrical engineer I'm able to run a mechanical simulation with the help of AI. It teaches me enough for me to understand what to do and to read the results.

Francoise von Trapp : 21:44

For a chip designer who has to think about not just the chips anymore, but how it's going to perform in the package and what the package is going to do to that chip. Is it the job of the EDA software tools to provide that information back? If you make this adjustment in your design, this is what it's going to look like at the end and feed that information back so they can adjust that accordingly.

Pratyush Kamal: 22:09

Yeah, All of the EDA vendors want to do that, are doing that.

Francoise von Trapp : 22:18

What we are trying to do now different is we want to do it more upfront.

Pratyush Kamal: 22:23

Right, right, okay, because the earlier you design these things in, the fewer problems you have down the road. Yeah, and 3D is very expensive, so you want to catch it even earlier than you did in 3D.

Francoise von Trapp : 22:28

Well, and that seems to be one of the motivations all the way around is that we've accepted the fact that this is a costly endeavor. And so how do we mitigate costs? You know, by improving the yields, by having the design determined way up front, all the way through the system. So for a designer of tools, for instance, you will have a background in chip design, but now you're working at an EDA company and you're relying on that experience you have from a design perspective to help develop the next tools, knowing what you, as a designer, need from an EDA tool right.

Pratyush Kamal: 22:59

That's correct.

Francoise von Trapp : 22:59

And it used to be. For instance, when I'd go to conferences, I would notice that you'd be at an advanced packaging conference and there wouldn't be any design companies there. They were at their own conferences, like you know DAC or DesignCon or whatever. But now you see there is all of the design houses are actually having a presence at conferences, speaking at conferences. There's design tool tracks now. So what do you, as an EDA company, need to know from the advanced packaging community? What kind of things do you need from them to succeed in developing the tools that they need?

Pratyush Kamal: 23:38

At the very basic. We need to understand the underlying package technology that the chip will employ and that will translate to what kind of interfaces we can put on the chip to connect them together. It will also define what kind of boundary conditions we'll see in terms of thermal, what other challenges we'll see. So the package, the choice of the material, the choice of interconnect technology within the package are very critical, and these are the two components really within the package. But it's not just about the package by itself. Package is being used to connect two chips now two chiplets, so you need more or more, yeah or more, and different functionalities different functionalities.

Francoise von Trapp : 24:21

You were talking about s ram before we also have other right like rf devices and all of that right yeah, analog and logic yeah in the past.

Pratyush Kamal: 24:30

When you look at a pcb, you have so many chips on the pcb and they talk to each other, right, but the communication is very slow because each chip is designed to work on its own. Of course, every chip requires some input data and that it uses to provide you with some output data. But all of that interface? Today on the pcb, everything is very structured, defined, there is a stack defined for it. But conversion of language from one stack to the other through the stack takes time, takes latency, takes area, takes power. When you put two chiplets into a package, you're trying to minimize that cost. That's the whole idea of putting things closer together. So now you have suddenly improved your data latency, you have improved your data power efficiency. You have suddenly improved your data latency. You have improved your data power efficiency, you have improved your data throughput.

Pratyush Kamal: 25:20

But that's not enough. You need to design them also in tandem together, because these chiplet by definition. You want to leverage resources from each other, right? So take the example of on-chip non-volatile memory. Why duplicate it across both chips when you can make do with one chiplet? Because it's expensive to add those flavors on a chiplet, and especially when we look at where the industry is headed. If you look at the UCI 2.0 spec, it talks about interoperability. The whole 2.0 spec is really built with that in mind. How do we enable open chiplet ecosystem? We are not just stopping at designing two chiplets together. We want to design a chiplet of tomorrow that can work with any chiplet from any third-party vendor as well.

Francoise von Trapp : 26:02

Yeah, that's why we have the UCIE right, the common interface, and there's a couple others. I think there's a bunch of wires is the other one.

Pratyush Kamal: 26:09

Bunch of wires is the other one. Ucie is the one getting the most traction currently because it really serves the need of high-performance computer applications out the door. As it was defined in 1.0 spec, they come with a lot of flavors. There are a lot of optional features. I think that the UCI may also become a tiered interface where you will have different layer level of certification.

Francoise von Trapp : 26:33

So just telling that I have a ucie compliance chip alone would not be enough for tomorrow you'll have to probably categorize what kind of ucie are you using, because of all the configuration flexibility you have there so I want to switch gears just a tiny bit to talk about one of my hot button items right now, which is the amount of power AI uses in training large language models and the stress that's going to be putting on the grid. Isn't there a role for EDA to play in helping to reduce that massive energy appetite of AI?

Pratyush Kamal: 27:12

Definitely. We had a role to play yesterday. We will have continued role to play. The more power becomes a problem, the bigger role we'll have, because every person that we save off a larger footprint is a massive saving in itself. We all saw Google's ex-CEO, eric Schmidt, recently made a statement that by 2030, he misspoke 99%, but it was actually 9.9% or something. So basically, usa's total energy consumption.

Francoise von Trapp : 27:39

Wait, he misspoke, it's not 99%.

Pratyush Kamal: 27:41

No, it's not.

Francoise von Trapp : 27:42

It's going all over the place.

Pratyush Kamal: 27:44

Yeah, it became a meme because the numbers he used they don't line up to 99. I was like 99 doesn't sound correct, that's huge. There's a big difference. It became a meme. Yeah, I know it's because they're still talking about tens of gigawatts, they're not talking about terawatt right If you look at the whole.

Pratyush Kamal: 28:00

US, as a country we are in terawatt probably, range EDA is becoming more and more critical to solving the data center power problem. First thing, first till now, when we design chips for data center applications, power was not our constraint. Thermal was our constraint our ability to draw thermal.

Pratyush Kamal: 28:22

Right right right Now they're very tightly coupled. More power means more thermal, so indirectly you were addressing power, but that was not the design constraint you gave to your chip. You gave a thermal constraint to your chip and a lot of early data center adapters benefited a lot from subsidized electricity. All over the world the need for data center is changing. We are talking about 10% of US electricity consumption will be in data centers by 2030. That's a big number. We are basing it based on the need of what we think the AI hardware need will evolve in the next five years, but things could accelerate beyond our comprehension because we are allowing the machines to make decisions for us. They're getting smarter by day, so there's an exponential snowball effect that, in terms of design complexity that may very soon arise, complexity that may very soon arise Once we have, let's say, learned to harness AI in terms of chip design, we won't stop at a trillion transistor design. We will aim to put the whole end-to-end system as a single entity.

Francoise von Trapp : 29:23

So when you talk about thermal, though you know, one of the things I've learned recently is that heat equals energy loss.

Pratyush Kamal: 29:31

Yeah.

Francoise von Trapp : 29:32

If you can reduce the energy loss, then it also impacts how much heat's being put out. Right, if you're, if you're making things more energy efficient, then it's going to impact that thermal footprint and reduce the amount of power that's actually used, because you're keeping all of that energy in use. It's not, you're not just expending it. Yeah, yeah, is that right? Did I say that right?

Pratyush Kamal: 29:56

That's right, yeah. The other reason suddenly the energy consumption in data centers became a centerpiece is because AI data centers in the last few generations started adopting desegregated designs. The designs became so big they started desegregating, so there was an added cost of cutting a monolithic die into two as well there. So I just wanted to add that as well.

Francoise von Trapp : 30:24

With chiplets, we are disaggregating right.

Pratyush Kamal: 30:28

Yeah.

Francoise von Trapp : 30:29

But we're also re-aggregating into one device and putting everything as close as possible to make them more efficient.

Pratyush Kamal: 30:37

Yeah.

Francoise von Trapp : 30:38

So chiplets are also a push towards that efficiency for AI.

Pratyush Kamal: 30:43

Yeah, yeah, individual chiplets are becoming more efficient by themselves, but you have the added overhead of connecting the two and you burn extra power there.

Francoise von Trapp : 30:52

Okay, so we've been talking a lot about how important the EDA industry is to semiconductor manufacturing. What role does Siemens play in providing 3D IC design tools to the industry?

Pratyush Kamal: 31:07

Siemens is playing a very central role. We are one of the three large organizations that have a whole suite of tools to realize your 3D design from concept to tape out. What we are doing currently is taking all of our silicon tools, all of our packaging tools, and we are not stopping there. We are looking at our mechanical design tools, for example, computational fluid dynamics. We are bringing all of these under a single umbrella. We are trying to see how we can stitch them together, how we can automate the data exchange across different tools by standardizing the language they speak, the information that needs to be passed on to a tool. For example, we are very familiar with the concept of design kits in the silicon world. Foundries provide the design kit and it becomes as a Lego piece to you and then you just put those Lego pieces together and build your chip. In the silicon world we did not follow that practice in packaging till now. Siemens is leading the effort here across the industry is trying to standardize that language. We don't want to read a PDF-based design rule manual and build a chip based on that. We want to automate that language. We want our tools one tool to understand the language of another tool, whether it's from Siemens or from Cadence or from Synopsys. So we are trying to make interoperability as a very central to our 3D IC workflows. We are creating loops between different tools and different workflows.

Pratyush Kamal: 32:33

What I mean by a workflow is basically a physical design. Workflow is essentially everything relating to physically designing that entity, whether it's a floor planning of the chip, floor planning of the package. How do you do the bump connections, how do you do the interposer or the substrate routing. It's all part of the physical design workflow. It doesn't stop there. Nothing is done until you verify it. So, of course, verification is also part of that workflow. So that's what I mean. So we are trying to create these workflows and stitch them together as well, Because when you are doing a physical design, you need to know thermal, you need to know your signal integrity implications. Power is always at the center of 3D ICs. I can't put the emphasis anymore on it.

Francoise von Trapp : 33:20

To wrap things up, can you summarize what you would want listeners to take away from this conversation? Maybe the three top points that you want to make here.

Pratyush Kamal: 33:31

I can promise my customers that, as a representative of the EDA industry, we understand your challenge as well as you do. We understand your complexity and that's why, philosophically, the EDA industry is starting to see the need for a solution-focused software than an isolated software by itself. The software by itself means nothing until it gives you a solution right. So we are also trying to enable an open-chiplet economy as an EDA industry representative, and that will allow our customers flexibility to use best-in-class tools. They won't be forced or obligated to use tools that they don't want to, but because they're part of that workflow today, they are forced to use certain tools. So we want to allow our users that flexibility tomorrow.

Pratyush Kamal: 34:27

And the third thing is, with AI available as a tool to us, we expect a future where our users will be able to work at a higher level of abstraction and because the workforce of tomorrow that we see is going to be consisting of experts with a very deep vertical domain focus, but more of a broad focus. And the last thing is what we understand is in the United States, the average age of a double E is 57. We need a lot, many more engineers to be able to do the work and, as you can see, it's really dominated by people who are very close to retiring, so we'll have even more labor challenge in future. So EDA industry, because that's where the design starts. So we are very focused on building workforce of tomorrow and we work very closely with the universities in terms of providing them educational software and training the next generation of engineers and creating excitement around EDA, 3d, ic and advanced packaging.

Francoise von Trapp : 35:35

So if they're learning to be a chip package designer in school right now, they could possibly be using the tools or learning on the tools that they're going to be using in the field. Yeah, okay, all right. Well, where can people go to learn more?

Pratyush Kamal: 35:50

Please visit us at wwwsiemenscom and you will learn about all the exciting technologies that we have for you to build your next generation chip.

Francoise von Trapp : 36:00

Okay, great. Thank you so much, Pariyush.

Pratyush Kamal: 36:03

You're welcome. Thank you, Frances.

Francoise von Trapp : 36:09

To explore how Siemens is shaping the future of 3DIC design, head over to siemenscom slash 3DIC and see how you can bring your next generation chip designs to life. And if you're listening prior to June 22nd and will be attending DAC, make sure to visit the Siemens booth on the exhibitor floor. There's lots more to come, so tune in next time to the 3D Insights podcast. The 3D Insights podcast is a production of 3D Insights LLC.